NOR Flash device is a type of non-volatile flash memory, which is characterized by the implementation of the chip. The application can be run in the flash memory directly without reading the code to system RAM (random access memory); thus it has higher transmission efficiency.
Referring to FIG. 1, a schematic cross-sectional view of a conventional NOR Flash device is shown, which includes a substrate 1, a gate dielectric layer 2, a floating gate 3, a laminated dielectric layer 4 (usually ONO layer), and a control gate 5, which are positioned on a substrate 1, successively. A source region and a drain region are provided on the substrate 1 at both sides of the floating gate 3, which are not shown because the figure only contains two dimensions.
During the manufacturing process of the NOR Flash device with a size of 0.13 μm or less, in order to decrease an area of the storage region while maintaining a appropriate device coupling ratio, referring to FIG. 2 through FIG. 6, a method according to the prior art usually includes: forming a gate dielectric layer (not shown) and a first polycrystalline silicon layer 101 successively on the substrate 1; forming a first hard mask layer on the first polycrystalline silicon layer, etching the first hard mask layer 102 to form a first opening 103; forming a second hard mask layer 104 on the first hard mask layer 102, the second hard mask layer 104 covers a bottom and a sidewall of the first opening; etching the second hard mask layer 104 to form a second opening 105 using a self-aligning process, a width of the second opening 105 is smaller than a width of the first opening; etching the first polycrystalline silicon layer to form a floating gate 106 using the self-aligning process. A laminated dielectric layer and a control gate are formed on the floating gate 106, which will not be further described.
In the conventional photolithography technique, the distance between adjacent float gates is reduced, such that an area of the storage region is decreased while maintaining the appropriate device coupling ratio. However, the NOR Flash device fabricated according to the prior art has a poor yield.